1. Field of Invention
This invention relates to an isolation structure and a device structure including the isolation structure, wherein the device structure may be a memory structure applied to a volatile or non-volatile memory apparatus.
2. Description of Related Art
A typical memory array, such as a DRAM or flash memory array, includes word lines and bit lines crossing the word lines, and may utilize vertical MOS transistors to achieve 4F2 cells. For the 4F2 cell of the next generation, the design of buried bit lines is important at least because of the simplified MOL (middle of line) process.
FIG. 1 illustrates a vertical-sectional view (a) and a transverse-sectional view (b) of the structure of a buried bit line and a corresponding vertical transistor in the prior art, wherein the sectional line A-A′/B-B′ corresponds to the part (a)/(b) of FIG. 1.
The buried bit line 102 includes a metallic layer 104 and a doped poly-Si layer 106 thereon in a trench 108 in a semiconductor substrate 100. The metallic layer 104 is separated from the substrate 100 by a dielectric layer 110, and a diffusion region 112 is formed in the substrate 100 beside the poly-Si layer 106 to serve as a source/drain (S/D) region. The trench 108 is formed between two conventional isolation structures 114 each including an insulator only, and filled up by an insulating material 116. Word lines 118 are disposed over the buried bit line 102 and separated from the channel region 100a of the vertical transistor by gate dielectric 120. The other S/D 122 of the vertical transistor is disposed over the channel region 100a. In the case of DRAM, the S/D region 122 is coupled to a capacitor (not shown).
For the diffusion region 112 is close to the isolation structure 114, the depletion region 140 thereof reaches to the border of the isolation structure 114 so that the channel region 100a becomes a floating body and the holes generated in the operation cannot be evacuated. Such floating body effect causes undesirable leakage current and greatly degrades the retention capability of the DRAM cell.